Physical Design Engineer

He/she should be able to help other junior engineers within the team.

This role is for a technical ladder and so it requires hands-on working knowledge preferably with SNPS tools like DC, PT, PT-SI and ICC2. Typically requires 4-7 years of experience after graduation from a reputed university.

Should be strong in technical concepts, fundamentals, and good team player. The role involves daily technical interaction with local, US counter parts. He/she will be part of SNPS DDR, HBM, UCIe IP implementation team and responsible for the implementation and integration of world class Die-to-Die IPs at the cutting-edge technology nodes (14nm,10nm,7nm,5nm and below). Timing closure above ~2GHz, mixed signal had macro-IP integration, Building the efficient clock trees with very tight skew balancing are some of the challenges as part of day-to-day job. Prior working knowledge in the DDR/HBM/UCIe timing closure, implementation would be an added advantage.