Have in-depth knowledge of the entire physical design process from RTL to GDS2 generation which includes floorplan, Placement, CTS, Routing, and Sign Off ( STA, PV, IREM)
Have hands-on experience in latest sub-micron technologies below 14nm.
Familiar with Physical Verification flows (DRCLVSEMIR)
Experience in ECO implementation
Hands on experience in PnR tools Synopsys ICC II Cadence Encounter etc
Familiarity with any of Scripting languages PERL, TCL
Should possess good Leadership Skills
Must have good communication & problem-solving skills.