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VLSI Trained Fresher
Open Silicon Research
posted 1mon ago
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Flexible timing
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Job Description
The Opportunity
We are looking for engineers who will be working in one of the following functions. RTL : Design, SoC Integration, SDC generation, RTL quality checks including Lint, CDC, RDC
Verification : Subsystem, SoC level, Test bench architecture, Test environment creation, test plan, test cases, regression, coverage, Assertions, scoreboards, checkers, monitors, We use System Verilog / UVM
Physical Design & Verification : which includes Synthesis, floorplan, Place & Route, Static Timing Analysis, Logical equivalence check, Glitch Noise Analysis, IR Drop, Power/Signal EM, PI/SI, DFM, ESD, Power analysis, clock duty analysis, ..
Design Methodology : setting up PD tool flow for latest technology node (5nm, 3nm, ..), analysis / comparison for technology nodes, understand impact of new design rules / new foundry requirements, debug / resolve tool & flow issues.
Eligibility:
BTech/MTech in Electronics/ /VLSI/Microelectronics Engineering 2025 passing out only with 70% throughout in academics and zero active backlogs.
Position - Intern Duration - 6-month/1 year internship
Employment Type: Full Time, Permanent
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Flexible timing
Monday to Friday
No travel
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