Support and Debug flow issues and testcases from Design teams for Simulation, corner setup, LVS, DRC, Fill, EMIR, post layout simulation, Parasitic Extraction for transistor level flow, PERC
Responsible for PDK download, setup, customization and flows definition
Responsible for assisting Tapeouts, final chip finishing runs, interface across foundry/customer for rulesets etc.
Train, Deployment and support of Automation flows to Design teams
Knowledge and hands-on experience in Schematic design and layout design environment. physical verification - DRC, LVS, DFM checks, Electrical verification like EMIR, ERC, PERC and Reliability Verification
Drive Interfacing between Digital and Analog/Mixed signal methodologies
Skills:
Good knowledge on scripting skills - TCL, Python, BASH, PERL, SVRF, SKILL (Cadence) etc.
Good knowledge on EDA Tools in Analog flow (Synopsys Custom Compiler/Cadence Virtuoso /Siemens EDA s Calibre/Ansys Totem)
Good understanding of standards and formats like Spice, CDL, LEF, DEF, Verilog, SPEF, GDS, OA, .LIB, etc.
Good knowledge of Version Control System and Data management aspects using SVN / ICManage / Git / Cliosoft / Perforce / Methodics etc.
Understanding of tool License features and license administration is a plus
What Youll Need:
Must possess a minimum of bachelor s degree in electronic engineering or related program
Must possess 5 to 8 years work experience as a CAD Automation engineer role.
Experience with different Technology Node (7nm, 5nm, 4nm, 3nm etc)
Experience with different foundry (TSMC, SAMSUNG etc) and design techniques would be an asset.
Personality - team player, good written and verbal communication, open to new ideas and quick learner