As a Senior RTL Design Engineer, you will be responsible for designing and implementing Register Transfer Level (RTL) descriptions of digital circuits for integrated circuit (IC) designs. You will be part of the hardware design team to develop and optimize RTL code for various digital components, ensuring functionality, performance, and compatibility with target hardware platforms.
Key Responsibilities:
Design and implement architecture, microarchitecture, and digital circuits, including hw-sw co-design and RTL coding. Create functional specifications and other design documents. Collaborate with the verification team to test, debug, and fix design bugs, and work with physical design teams to ensure efficient design closure and implementation of late design changes. Additionally, create and maintain clear and detailed design documentation, including specifications, design guides, and coding standards.
Technical Leadership: Lead architecture definition and feature specification of IP and/or submodules to enable development of benchmark solutions for current and future markets. Study and analyse emerging trends in technology and contribute to creating future product roadmap. Mentor and guide junior engineers in design tasks.
Collaboration: Work closely with cross-functional teams, including verification, physical design, and software development teams, to ensure the successful integration of digital designs.
Continuous Learning: Stay updated with industry trends, new technologies, and implement best practices related to digital design and RTL coding.
Requirements:
Bachelors or Masters degree in electrical/Electronics Engineering, Computer Engineering, or a related field.
Extensive expertise of 8+ years as RTL Engineer.
Solid understanding of digital design concepts, computer architecture, and hardware description languages (Verilog or VHDL).
Experience in complex digital designs like CPU/DSP core pipelines, cache coherence protocols, network on chip is advantageous.
Familiarity with digital design tools and workflows, including simulation and synthesis tools.
Knowledge of industry-standard protocols and interfaces (AXI, TileLink, PCIe, DDR, etc.) is advantageous.
Experience with timing analysis and closure techniques is a plus.
Strong problem-solving skills and attention to detail.
Good communication and teamwork skills.
Ability to work independently and collaborate in a fast-paced engineering environment.
Passion for learning and a proactive attitude towards acquiring new skills.