Asic Rtl Design Engineer

Job description

RTL Design Engineer

Job Location: Bangalore

This role offers a position in Digital Design working on IP subsystem and cores targeted to a variety of industry leading SoCs. Key Responsibilities

• Develop micro-architecture and RTL design for Cores related to security. Responsible for block level design.
• Micro architecture and enabling SW teams to use HW blocks.
• Running ASIC development tools including Lint and CDC.
• Report status and communicate progress against expectations.

Minimum Qualifications

• Bachelor's degree in Engineering
• 7+ years Hardware Engineering experience or related work experience.

Preferred Qualifications

• 7 to 12 years of work experience in ASIC/SoC Design
• Experienced in RTL design using Verilog / System Verilog.
• Knowledge of cryptography, public/private key, hash functions, random number generator, encryption/signatures algorithms (AES, SHA, GMAC, etc.)
• Knowledge and experience in Root of Trust and HW crypto accelerators will be a plus.
• Knowledge and experience of defining HW/FW interfaces.
• Experienced in Linting, CDC and LEC.
• Experienced in database management flows with Clearcase/Clearquest.
• Ability to program effectively in Verilog, C/C++, Python, Perl
• Excellent oral and written communications skills
• Proactive, creative, curious, motivated to learn and contribute with good collaboration skills.

Educational Requirements - Required:Bachelor's, Electrical Engineering Preferred:Master's, Electrical Engineering