Functional Verification Engineer - System Verilog

Responsibilities :

- Develop and execute comprehensive verification plans for complex IP blocks and SoCs, including microarchitecture, functional, and performance verification.

- Design and implement high-quality testbenches using industry-standard methodologies (e.g., UVM, OVM).

- Develop and maintain test suites, including directed tests, constrained random tests, and coverage-driven tests.

- Debug and troubleshoot complex verification issues, analyze simulation results, and identify root causes of failures.

- Collaborate closely with design engineers, architects, and other verification engineers to ensure timely and successful chip delivery.

- Participate in design reviews and contribute to the design process.

- Stay abreast of the latest verification methodologies, tools, and industry trends.

- Document and report on verification progress, issues, and risks.

Qualifications :

- 4-7 years of professional experience in functional verification of complex digital designs (IP/SoC).

- Strong understanding of digital design fundamentals and verification methodologies.

- Expertise in developing and executing testbenches using industry-standard methodologies (e.g., UVM, OVM).

- Experience with SystemVerilog, C/C++, and scripting languages (e.g., Perl, Python).

- Good understanding of cache coherency protocols.

- Experience with high-speed protocols (e.g., PCIe, DDR, Ethernet) is a plus.

- Experience with UPF (Unified Power Format) and low-power simulation is a plus.

- Excellent problem-solving, analytical, and debugging skills.

- Strong communication and interpersonal skills.

- Bachelor's or Master's degree in Electrical Engineering, Computer Science, or a related field.