12 Kinara Jobs

Who we are

Kinara is a Bay Area-based venture backed company

Our architecture is based on research done at Stanford University by Rehan Hameed and Wajahat Qadeer under the guidance of legendary Prof

Mark Horowitz (http://www-vlsi

stanford

edu/~horowitz/) and Prof

Christos Kozyrakis http://csl

stanford

edu/~christos/)

What we do

Our game-changing AI solutions revolutionize what people and businesses can achieve

Ara inference processors combined with our SDK deliver unrivaled deep learning performance at the edge to accelerate and optimize real-time decision making where every millisecond is critical, and power efficiency is a must

Kinara solutions embed high-performance AI into edge devices to create a smarter, safer, and more enjoyable world

Edge AI is on the brink of a boom, and Kinara is looking forward to playing a significant role in it

About The Role

We are seeking a talented Implementation Engineer to join our dynamic team

The successful candidate will be responsible for leading and executing Synthesis and STA for complex AI SOC with multi-mode and multi power domain design, ensuring the quality and reliability of our products

This is what you are responsible for

Synthesis and STA (static timing analysis)

Ability to optimize designs for best in class in low power and high performance with logically equivalent RTL

Professional experience with ECO implementation, both functional and timing closure

Experience with multi-clock, multi-power domain designs and multi-mode timing constraints

Familiarity with DFT insertion

Familiarity with simulation, debugging tools, and working closely with Design teams

Ability to collaborate with different functional teams like RTL Design, DFT and Physical design

Showcase your deep understanding of the following physical design concepts/constraints: floor-planning, placement, congestion, and setup/hold timing closure

Necessary Qualifications

Bachelors or Masters degree in Electronics, Computer Science Engineering, or a related field

Minimum of 5 to 7 years of experience in Implementation flows/ Synthesis and STA

Experience with Cadence, Synopsys and Mentor tools

Experience with Verilog and VHDL

Experience with sign-off Static Timing Analysis, Logic equivalency checks, and Static Low Power Checks (UPF/CPF/CLP)

Formal verification for RTL 2 gates and gates2gates

Conformal ECO for doing complex functional ECOs

Low power synthesis on smaller blocks and subsystems using DC/Genus

Physical Aware synthesis

Writing Timing Constraints sub-blocks and Top level

Flow Automation and Scripting using TCL and Python or Perl

Work culture

We at Kinara have an environment that fosters innovation

Our team has technology experts who understand the big picture and mentors who coach passionate professionals to work on the most exciting challenges

We share responsibilities in everything we do, where every point of view is valued

Join us!

Now tell us your story

We are looking forward to reviewing your application

Make your mark!