SOC Physical Design Engineer Lead/Manager

The Client Development Group is looking for a highly motivated Physical Design Execution Lead/Manager to join the backend design team for the next generation of Complex Client SOC.In this position, you will be responsible for managing and working on all aspects of physical design activities of Intel's SoCs in lower technology nodes.Candidate will have multiple responsibilities including leading a high performing team of BE engineers and/or driving the complete project execution of complex SOC designs in leading edge process technologies on an aggressive schedule by working with global stakeholders including Arch, RTL, DFX, CAD team and EDA vendors.The candidate will be responsible for working with senior management in the organization to plan for and execute complete client SOC projects in physical design. This role also requires transparent and clear communication and mindset to excel at work in collaborative environment with teams in other domains and Geos.

Qualifications

Qualifications:

• Candidate must have 8 to 12 years of relevant experience with master's degree (M. Tech / MS) in Microelectronics/ Electronics Engineering or equivalent qualification from reputed institute.
• Candidate should have worked on full chip and partition level BE design using industry standard tool.
• Candidate should have good knowledge of Floor planning, Power planning, Placement, Clock Tree Synthesis and Routing.Candidate should be well versed with multiple optimization options for design closure and expected to guide and provide solution to team for complex implementation issues.
• Candidate should have good understanding of timing concepts and expected to analyze the constraint used for design and its impact on timing closure.
• Candidate should have worked on Layout closure for the blocks, ensuring DRC, LVS, density and Antenna requirements are met as per specification.
• Candidate should have good knowledge of top-level Integration issues to ensure block level deliverables meet project level requirements for timing and layout closures.
• This role requires good understanding of analysis and sign off flow for project.
• Candidate is expected to participate in the development and improvement of physical design methodologies and flow automation for achieving better execution efficiency.
• Candidate should have good knowledge of VLSI, Digital electronics and understanding of semiconductor devices, circuits, timing closure of digital design.
• Understanding of fabrication and process technology will be added advantage.
• Leadership experience in full chip SOC physical design with sign off for Tape out with silicon success is preferred

The SOC physical design Lead will exhibit behavioral traits that demonstrate:

• Strong communication and collaboration skills, including a willingness to work in diverse and collaborative environment with teams in different domains and Geos.
• Willingness to lead teams and influence cross-functional teams.
• Good analytical, problem-solving skill for debugging issues faced at work.
• Experience in leading teams through setting goals, schedule and staging plans along with tracking and enabling execution for team.