SOC Design Verification Engineer

Responsible for understanding the micro level architectural details of the design, preparing good test plans, developing re-usable test bench components.

Executing test plans and reporting bugs to have a flawless designs. Responsible for executing both RTL verification and GLS activities.

Qualifications
Required Skills :Test bench architecture and bus functional models development.

Proficient in coding Pre-Silicon functional validation tests to verify design to meet spec. requirements.

Creates efficient test plans for RTL validation and Gate level simulations.

Expertise in verification of design blocks (IP) and Subsystems for SoC(s).

Expertise in SoC level validation.

Expertise in System verilog , UVM, and/or OVM based verification methodologies.

Experience in OOPs concepts, coverage driven constrained random validation.

Good knowledge on AMBA standards (OCP, AXI, AHB, APB).

Working knowledge of scripting, SVA.

Looking for highly motivated individuals and ability to deal with ambiguity.

Experience :Bachelors or Master degree with 4+ years of relevant industry experience.