Sr ASIC Design Engr

• Perform physical implementation steps including floor planning, place and route, power/clock distribution for congestion analysis and timing closure at block level as well as full chip
• Work with logic designers to drive feasibility studies and explore design trade-off for physical design closure
• Perform technical evaluations of vendor, process nodes and IP and provide recommendations
• Develop physical design methodologies and automation scripts for various implementation steps from Synthesis to GDSII
• Perform static timing analysis, create timing constraints and validation, critical path analysis, timing closure and timing sign-off
  

Education & Experience Necessary For Success:

• 2+ years of experience in ASIC physical design flow and methodologies in 5/7nm and 16nm process nodes
• Has solid knowledge of full design cycle from RTL to GDSII and understanding of underlaying concepts of IC design, implementation flows and methodologies for deep submicron design
• Experience with EDA Place & Route tools like ICC2 or Innovus or similar tools and Timing tools like Primetime or similar
• Scripting experience in TCL, python or perl
• Candidates must have a Bachelors Degree or higher in Electrical/Electronics and Communication / VLSI / Microelectronics with very good academics ..