Sykatiya Technologies - FPGA & Emulation Engineer - RTL/Netlist (5-8 yrs)

KEY RESPONSIBILITIES :

1. BE/MTECH with 5 to 7 years of experience in Emulation/ FPGA Prototyping models Creation from RTL / Netlist.

2. Defining and documents RTL changes required for Emulation/FPGA.

3. Develops hardware and software collaterals and integrates it with the Emulation model.

4. Developing emulation test benches to support necessary DV scenarios is an added advantage.

5. Emulation model bring-up and emulation verification experience at SoC level.

6. Create test plans, write and debug tests for functional verification and emulation platforms.

7. Developing and applies automation aids, flows and scripts in support of emulation ease of use and increase the process efficiency.

8. Experience in debugging failures using Verdi, log files and waveform dump is mandatory.

PREFERRED EXPERIENCE:

1. Knowledge of x86 and/or ARM SoC Architecture.

2. Emulation experience with one or more ZeBu, Palladium, Veloce Emulators and FPGA Prototyping Platforms.

3. RTL migration, Partitioning, Synthesis, PnR and timing analysis of SoC RTL on industry standard prototyping and emulation platforms.

4. Knowledge of one or more protocols; Ethernet, USB, PCIe, DDR, Low and High speed protocols, AMBA BUS protocols.

5. Experience with SoC boot flow, clocking, Reset and platform bring up in Emulators is desired.

6. Experience with Power management flows is an added advantage.

7. Experience in developing C/C++, Python test content.

8. Experience with System Verilog Assertions with industry standard tools a plus

9. Experience in developing System Verilog based test content.