- Verification of SerDes Designs: Develop and execute verification plans and testbenches for SerDes IPs (Intellectual Property) and subsystems to ensure they meet functional and performance requirements.
- Testbench Development: Design and implement verification testbenches using industry-standard verification methodologies (e.g., UVM, SystemVerilog, VHDL).
- Simulation and Debugging: Perform simulations, analyze results, and debug issues related to timing, protocol errors, and other design anomalies in SerDes blocks.
- Performance Evaluation: Evaluate and validate performance characteristics of SerDes systems including jitter, bit error rates (BER), signal integrity, eye diagrams, and other key metrics.
- Protocol Compliance Testing: Verify adherence to relevant SerDes protocols such as UCIe , PCIe, Ethernet, USB, DDR, DisplayPort, or custom protocols.
- Automated Testing: Develop automated regression tests to ensure the robustness and stability of the SerDes design over multiple versions and iterations.
- Collaboration: Work closely with the design, hardware, and software teams to troubleshoot issues, implement fixes, and verify design changes.
- Documentation: Create detailed reports and documentation on verification results, test scenarios, and issues found during testing.
- Continuous Improvement: Provide feedback for design and verification process improvements and contribute to innovation in verification strategies and methodologies.
- Experience:
- 8+ years of experience in SerDes verification or high-speed communication verification.
- Strong hands-on experience with verification methodologies such as UVM, SystemVerilog, or other simulation-based verification tools.
- Knowledge of high-speed serial protocols such as UCIe , PCIe, Ethernet, USB, DDR, or custom protocols.
- Experience in analyzing and interpreting signal integrity issues, jitter, BER, and eye diagrams.
- Skills:
- Solid understanding of SerDes architectures, link training, and equalization.
- Strong debugging skills, with the ability to work across multiple domains (timing, protocol, performance).
- Familiarity with hardware description languages (HDL) like VHDL or Verilog.
- Strong analytical, problem-solving, and communication skills.
- Experience with DDR protocol (e.g., DDR3, DDR4, DDR5) for memory interface verification.
- Understanding of UCIe protocol and its role in chiplet-to-chiplet communication.
Preferred Skills:
- Experience with Python, Perl, or similar scripting languages for automation.
- Exposure to high-speed memory interface design and verification, including DDR controller IP verification.
- Functional coverage, assertions knowledge in SV/UVM.
- Ability to work in a fast-paced environment and manage multiple verification tasks.
- Strong team player with good interpersonal and communication skills.
Employment Type: Full Time, Permanent
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