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Verification Engineer Lead - UVM/System Verilog (10-15 yrs)

10-15 years

Bangalore / Bengaluru

Verification Engineer Lead - UVM/System Verilog (10-15 yrs)

D2N Solutions

posted 2mon ago

Job Role Insights

Flexible timing

Job Description

SALARY : 20LPA - 45LPA


We are recruiting One of Our Indian Based MNC Client

Client - Indian Based MNC Client

Type of Job - Full Time/Direct hire

Type - Hybrid

Notice Period - Not more than 45 Days with serving candidates

Role : Verification Engineer Lead

Experience : 10+ Years

Locations : Bangalore


Mandatory Skills : SVM, UVM, System Verilog

Job Title : Verification Engineer Lead

Job Overview :

As a Verification Engineer Lead, you will be responsible for leading and managing the verification efforts of complex hardware and software systems. This role involves overseeing the development of test plans, verification methodologies, and ensuring that designs meet all required functional and performance specifications. The Verification Engineer Lead collaborates with cross-functional teams including design, architecture, and validation to deliver high-quality and reliable products. Your leadership will ensure that all verification processes are executed efficiently, and that any defects are identified and addressed early in the development cycle.

Key Responsibilities :

Verification Strategy & Planning :

- Define and lead verification strategy and methodologies for SoC, ASIC, or FPGA designs.

- Develop and oversee comprehensive test plans, ensuring all design specifications and requirements are met.

- Coordinate and schedule verification efforts, tracking progress against key milestones.

Technical Leadership :

- Lead a team of verification engineers, providing guidance, mentorship, and technical expertise.

- Ensure the team follows best practices and leverages industry-standard tools and techniques for verification.

- Review and contribute to design documents and specifications to ensure proper verification coverage.

Test Development & Automation :

- Develop and review verification test benches using tools such as UVM (Universal Verification Methodology), System Verilog, or VHDL.

- Automate test suites for regression testing and track test results to ensure comprehensive coverage.

- Identify and implement improvements in test automation frameworks.

Simulation & Debugging :

- Lead efforts in running simulations, analyzing results, and debugging complex issues in the design.

- Work closely with design engineers to resolve any issues identified during verification.

- Use simulation tools and environments (e.g., ModelSim, VCS, Questa) to validate designs.

Functional Coverage & Metrics :

- Define and monitor functional coverage metrics to ensure design validation completeness.

- Track and report on key verification metrics such as coverage, bug density, and simulation time.

- Ensure the team meets functional coverage goals and adheres to verification timelines.

Cross-functional Collaboration :

- Work closely with design, system architecture, and validation teams to understand the design intent and identify potential verification challenges early.

- Collaborate with software and hardware teams to verify integration between different subsystems.

- Communicate verification progress and issues clearly with stakeholders and management.

Documentation & Reporting :

- Maintain thorough documentation of verification strategies, test cases, and results.

- Provide detailed reports and recommendations on design quality and readiness for the next development phase.

- Lead post-verification reviews and retrospective sessions to continuously improve processes.

Required Skills & Qualifications :

Technical Expertise :

- Strong experience in verification of SoC, ASIC, FPGA, or embedded systems.

- Proficiency in SystemVerilog, VHDL, and UVM or other verification methodologies.

- Experience with simulation tools like VCS, ModelSim, Questa, etc.

- Solid understanding of digital design principles, functional verification, and low-power design techniques.

- Familiarity with scripting languages such as Python, Perl, or Tcl for automation.

Leadership & Management :

- Proven track record of leading and managing teams of verification engineers.

- Strong project management skills, including the ability to plan, prioritize, and meet deadlines.

- Excellent problem-solving and debugging skills, with attention to detail.

Soft Skills :

- Strong verbal and written communication skills.

- Ability to work effectively in cross-functional teams.

- Leadership qualities including mentorship, decision-making, and conflict resolution.

Preferred Qualifications :

- Experience with formal verification techniques and tools.

- Experience with emulation and FPGA prototyping.

- Knowledge of SystemC, C/C++, and high-level synthesis tools.

- Experience in low-power design verification.

- Master's or PhD in Electrical Engineering, Computer Engineering, or a related field.

Education & Experience :

- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.

- 7+ years of experience in hardware verification with at least 2-3 years in a leadership role.

Note - Please share an updated copy of your resume while replying to this email with the below information.Interested Candidates

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Verification Engineer Lead-?

SVM-?

UVM-?

System Verilog-?


Functional Areas: R&D

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