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23 Cyient Jobs in Pune

Technical Lead: Analog Design

8-13 years

₹ 60 - 95L/yr

Hyderabad / Secunderabad, Pune, Bangalore / Bengaluru

12 vacancies

Technical Lead: Analog Design

Cyient

posted 23hr ago

Job Role Insights

Flexible timing

Key skills for the job

Job Description

Dear Applicants


We, Cyient is hiring for Technical Leader: Analog Design for End to End Offshore-Onshore Model based Global Product R&D from scratch-based Opportunity.


Base Location: Bangalore, Pune & Hyderabad

Experience Range: 8-15 Yrs


Key Skills:

  • The candidate should have experience in Analog and Mixed Signal Design with focus on PMIC blocks such as DC-DC converter (BUCK,BOOST), LDOs and clocking circuits. Strong fundamentals of CMOS design, and active filter design. The various task involves, circuit design, validation, mixed signal validation, and reliability validation.
    Exposure to PMIC designs High speed digital circuit design and analysis with timing and flow closure. Digitally assisted analog circuit and techniques. The candidate will be responsible for the High speed, low power, and reliable analog and digital circuits for various areas of PLL. Good knowledge of control systems, Bandgap reference, bias, op-amps, feedback and compensation techniques.
  • You will be joining an expanding analog/mixed-signal circuit design team involved in design and development on cutting-edge foundry process development nodes.
  • Your responsibilities will include but not be limited to:
  • The candidate should have experience in Analog and Mixed Signal
  • Design with focus on Analog blocks and clocking circuits. Strong fundamentals of CMOS design, passive RC circuits, switched cap circuits are a must for this role
  • The various task involves, circuit design, validation, mixed signal validation, and reliability validation.
  • High speed digital circuit design and analysis with timing and flow closure. Digitally assisted analog circuit and techniques.
  • The candidate will be responsible for the High speed, low power, and reliable analog and digital circuits for various areas of PLL. Good knowledge of control systems, band gaps, bias, op-amps, LDOs, feedback and compensation techniques. Experience in LC VCO/DCO design.
  • Good exposure to performance parameters of VCO as well as complete PLL architecture.

Interested AMS Design Specialists, kindly share updated CV to rajanikant.sharma@cyient.com for detailed discussion.


Thanks and Regards

Rajani Kant Sharma

Sr Recruiter: Global Lateral Hiring: Semicon Vertical

Cyient


Employment Type: Full Time, Permanent

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Cyient Interview Questions & Tips

Prepare for Cyient Technical Lead roles with real interview advice

Top Cyient Technical Lead Interview Questions

Q1. Design an weather app using android architecture components?
Q2. What is difference between c and c++
Q3. Tell me how pointer works in c
View all 6 questions

What people at Cyient are saying

3.5
 Rating based on 74 Technical Lead reviews

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Read 74 Technical Lead reviews

Technical Lead salary at Cyient

reported by 583 employees with 8-15 years exp.
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₹7.4 L/yr - ₹28 L/yr
5% less than the average Technical Lead Salary in India
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What Cyient employees are saying about work life

based on 4.5k employees
63%
93%
57%
88%
Flexible timing
Monday to Friday
No travel
Day Shift
View more insights

Cyient Benefits

Team Outings
Soft Skill Training
Cafeteria
Job Training
Health Insurance
Work From Home +6 more
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Cyient Hyderabad / Secunderabad Office Locations

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Hyderabad Office
Headquarter
Cyient Ltd. - Uppal, NSL SEZ ARENA, 9th Floor, Block-6, Survey No-1, Plot No. 6, Uppal - Ramanthapur Rd, Uppal Hyderabad
Telangana 500039
Hyderabad Office
Cyient Ltd, Plot no-2, IT Park,ISB Road, Nanakramguda, Gachibowli, Near Continental Hospital Hyderabad
Telangana 500032

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