We are seeking an experienced and highly skilled Senior VHDL/Verilog Engineer with 6-8 years of hands-on experience in designing, developing, and testing FPGA and ASIC designs. The ideal candidate will have expertise in handling high-speed protocols such as JESD, 10G Ethernet, and PCI interfaces, as well as experience with FPGA and processor VHDL drivers. This role requires a deep understanding of digital design, a proven track record of successful projects, and the ability to lead and mentor junior engineers.
Key Responsibilities 1. FPGA/ASIC Design
Lead the design, implementation, and verification of complex digital circuits using VHDL and/or Verilog.
Develop and maintain FPGA/ASIC designs for various applications.
Perform synthesis, place and route, and timing analysis using industry-standard FPGA tools.
Ensure designs meet performance, power, and area requirements.
2. High-Speed Protocols
Design and implement interfaces for high-speed protocols such as JESD204B/C, 10G Ethernet, and PCI, Aurora protocol transfer, DMA transfer between PL and PS.
Optimize designs for high-speed data transfer and signal integrity.
Troubleshoot and resolve issues related to high-speed protocol interfaces.
3. FPGA and Processor VHDL Drivers
Develop VHDL drivers for FPGA and processor interfaces.
Integrate VHDL drivers with other system components.
Validate and test VHDL drivers in real-world applications.
4. Simulation and Testing
Write and execute comprehensive testbenches to verify design functionality.
Use advanced simulation tools to debug and validate designs.
Perform functional and timing simulations.
Implement and oversee advanced testing methodologies, including unit testing, integration testing, and system-level testing.
Conduct hardware debugging and validation on FPGA boards.
5. Documentation
Optimize designs for performance, power, and area.
Troubleshoot and resolve issues related to design, implementation, and testing.
6. Collaboration and Leadership
Collaborate with cross-functional teams, including hardware, software, and systems engineers, to integrate FPGA/ASIC designs into larger systems.
Lead design reviews and provide mentorship and guidance to junior engineers.
Act as a technical expert and resource within the team.
7. Optimization and Troubleshooting
Optimize designs for performance, power, and area.
Troubleshoot and resolve complex issues related to design, implementation, and testing.
Qualifications
Education : Bachelor s degree in Electrical Engineering, Computer Engineering, or a related field. A Master s degree is a plus.
Experience: 6-8 years of experience in FPGA/ASIC design using VHDL and/or Verilog.
Technical Skills:
Extensive experience with VHDL and/or Verilog HDL.
Proficiency with FPGA design tools such as Xilinx Vivado, Altera Quartus, and Lattice Diamond.
Deep knowledge of digital design principles and methodologies.
Advanced proficiency with simulation and verification tools like ModelSim, QuestaSim, and Xilinx ISE Simulator.
Experience with synthesis and timing analysis tools like Synopsys Design Compiler and Cadence Genus.
Expertise in handling high-speed protocols such as JESD, 10G Ethernet, and PCI.
Experience in developing FPGA and processor VHDL drivers.
Strong understanding of hardware description languages and digital circuit design.
Soft Skills:
Strong analytical and problem-solving skills.
Excellent communication and leadership abilities.
Detail-oriented with a focus on quality and accuracy.
Ability to manage multiple tasks and meet deadlines.
Proven ability to lead and mentor junior engineers.
Preferred Qualifications
Knowledge of embedded systems and firmware development.
Familiarity with scripting languages (e.g., System Verilog).
Experience with version control systems (e.g., Git).
Experience with high-speed design and signal integrity analysis.