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Design Engineering Architech
Apex Semiconductor
posted 8hr ago
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Job Description
Design and implement DFT IP w/ Verilog/SystemVerilog and/or VHDL
- Design and implement RTL for DFT IP incl. POST, IST
- Develop synthesis automation for DFT IP including synthesis and timing constraints, RTL insertion and verification
- Own and maintain, extend, and enhance existing DFT IP like LBIST
Employment Type: Full Time, Permanent
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Anonymous · Hardware
in Bengaluru
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No help, only unnecessary pressure. Lowering confidence.
Read 3 reviewsDesign Engineer salary at Apex Semiconductor
reported by
5
employees
₹7
L/yr - ₹9.2
L/yr
62%
more
than the average Design Engineer Salary in India
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What Apex Semiconductor employees are saying about work life
based on 6 employees
Flexible timing
Monday to Friday
No travel
Apex Semiconductor Benefits
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