Analog Circuit Design Engineer

Candidate will be joining an expanding high speed IO design team involved in design and development of next Gen memory interface PHY on cutting-edge process nodes.Responsibility will primarily include ownership of various task involves : circuit design, validation, layout review, mixed signal validation, behavioral modelling and reliability validation.Candidate will also be responsible for contributing to package and platform design guideline development.

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

• Candidate should possess 3+ year of experience with at least a Master degree in Electrical Engineering or equivalent.
• Strong fundamentals of CMOS design, RC circuits, high speed circuit design concept are a must for this role
• Candidate should have experience of designing high speed IO circuits (SerDes, LPDDR, DDR, HBM) such as transmitter, receiver, clocking, PLL, DLL etc.

Added advantage

• Exposure to high speed digital circuit design and analysis with timing and flow closure.
• Digitally assisted analog circuit and techniques.
• Experience with tools like Spectre, PrimeSim, HSPICE , Virtuoso, ADE and Custom Compiler or equivalent schematic and layout editor tools, Knowledge of DRC, LVS, and post-layout extraction tools
• Familiarity with Simulation tools (EMX, HFSS, Helic, Momentum) to execute SI-PI simulations is required.
• Experience with performing measurement, and correlating measurements to simulations.
• Experience with modeling and simulation of high-speed interface interconnects/channel
• Excellent analytical and problem-solving skills