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Premium Employer

Advanced Micro Devices

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3.8

based on 236 Reviews

147 Advanced Micro Devices Jobs

Sr. Silicon Design Engineer

Advanced Micro Devices, Inc

3.8

based on 236 Reviews

3-9 years

Hyderabad / Secunderabad

1 vacancy

Sr. Silicon Design Engineer

Advanced Micro Devices

posted 1mon ago

Job Role Insights

Flexible timing

Key skills for the job

Social Work VLSI Automation Testing Recruitment Motion Graphics Basic

+ 2 more

Job Description

We are looking for an adaptive, self-motivative design verification engineer to join our growing team. As a key contributor , you will be part of a leading team to drive and improve AMDs abilities to deliver the highest quality, industry-leading technologies to market. The V erification Engineering team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development.

THE PERSON:

You have a passion for modern, complex SOC architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/ time zone s . You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

Job Description:

The verification team is looking for a Senior Design Verification Engineer to contribute on the verification of Network on Chip IPs, Subsystems having adequate knowledgeble on the boot flow. The individual will help architect, develop and use simulation and/or formal based verification environments, at block, subystem , Fulchip level, to prove the functional correctness of Network-On-Chip (NOC) IPs, subsystem and SOC designs.

Responsibilities:

Plan verification of complex digital design blocks by fully understanding the architecture and design specification
Interact with architects and design engineers to create a comprehensive verification testplan
Design and architect testbenches in System Verilog and UVM to complete verification of the design in an efficient manner
Create and enhance constrained-random and/or directed verification environments, and formally verify designs with System Verilog Assertions (SVA) and industry leading formal tools
Debug tests with design engineers to deliver functionally correct design blocks
Identify and write coverage measures for stimulus quality improvements
Perform coverage analysis to identify verification holes and achieve closure on coverage metrics

General requirements:

Experienced with development of UVM, OVM, VMM and/or System Verilog, Verilog test benches and usage of simulation tools/debug environments like Synopsys VCS, Cadence IES to test block level/full chip SOCs and FPGAs
Strong understanding of state of the art of verification techniques, including assertion and coverage-driven verification
Strong understanding of different phases of ASIC and/or full custom chip development is required
Experience in block level NOC (Network on Chip) verification is a plus
Verification Experience in protocols like AXI3/4, DDR4/5, HBM, PCIe, Processors, Graphics is a plus
Experience as a verification architect, establishing the verification methodology, tools and infrastructure for high performance FPGAs, SOCs and/or VLSI designs is a plus
Experience with gate level simulation, power verification, reset verification, contention checking, abstraction techniques is a plus
Familiarity with verification management tools as well as understanding of database management particularly as it pertains to regression management is a plus
Experience with formal property checking tools such as Cadence (IEV), Jasper and Synopsys (VC-Formal, Magellan) is a plus

Special Requirements :

Architect and implement verification environment using advanced verification methodology such as UVM or SystemVerilog;
Test plan development and test writing;
Analyzing and debugging failures using simulation tools such as Synopsys VCS or DVE to verify hard IPs, FPGA fabric or System-on-Chip;
Functional coverage writing, coverage collection and analysis, coverage closure;
Writing System Verilog assertions and assertion based verification; and,
Running regressions, automation using scripting languages such as PERL and verification closure