Manager Silicon Design Engineering

Technical Expertise :

Fair understanding of Processor based SoC Design Verification is required.

Prior work experience of working on PCIe/CXL/USB/SATA IPs at IP Level or Sub-System Level Verification is a plus.

Strong background of MIPS/X86/ARM Processor based IP/Sub-System Level Verification is desired.

Know-How about SOC Micro-Arch flows (Reset, Boot flow, Cache/Coherency, System Memory) is desired.

Testbench Expertise :

Good understanding on Testbench Concepts, strong hands-on expertise in SV/UVM is must.

Developing and improving SV/UVM based testbench for functional verification of Processor and its components.

IP/Sub-System Verification background with Processor based Testbench is a must.

Good debugging skills using Simulator Waveform/Trace logs is required.

Prior exposure of working with any ISA simulator model based verification is a plus.

Protocols :

Fair understanding on protocols : AXI3/ACE/CHI is must.

Prior work experience on High-Speed Serials - PCIe/CXL/USB/SATA/GT IPs is preferred.

People Skills :

• Self-motivated and adaptable to fast-moving design verification environment.
• Willing to take up additional responsibilities to contribute to the team s success.

Role and Responsibilities :

• Will be part of Server SOC Verification Team working at AMD Hyderabad/ Bangalore, India.
• Responsible for Developing testbench components for SOC Design Verification.
• Writing/Enhancing BFM/Checkers/Monitors/Other-SOC Verif Envs.
• Bringing up Testbench with comprehensive verification plan and implementation of test cases.
• Work with a cross geographic teams, IP/SOC-Architects, Design Verification Stakeholders, ensure required Verif Env exists for verifying Design of Next-Gen Server architecture.

• Manager with ~3-4 years of managerial experience . SOC Integration know-how