1.1. What is difference between combination logic circuit and sequential combination logic? 2. What is the difference between synchronous reset and asynchronous reset? 3. Why we used FSM ? 4. Difference Between Mealey and Moore FSM . 5. What is setup time, hold time , metastability? 6. How can we remove metastability ? 7. What is clock domain crossing? 8. He asked about project ( Mtech only) 9. What is the difference between blocking and non blocking assignment in Verilog? 10. He gives some Verilog program ( using blocking and non blocking assignment) he asked minimum number of flip flop required? 11. What is gray counter ? 12. What is carry look ahead adder?

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Overview of digital circuit concepts and design principles in electronics.

Combination Logic Circuit: Output depends only on current inputs (e.g., adders, multiplexers).
Sequential Logic Circuit: Output depends on current inputs and past states (e.g., flip-flops, counters).
Synchronous Reset: Reset signal is synchronized with the clock; changes occur at clock edges.
Asynchronous Reset: Reset signal can change the state at any time, independent of the clock.
Finite State Machines (FSMs) are used for controlling sequential logic and managing states in digital systems.
Mealy FSM: Output depends on current state and input; can react faster to inputs.
Moore FSM: Output depends only on the current state; more stable but may react slower.
Setup Time: Minimum time before the clock edge that data must be stable.
Hold Time: Minimum time after the clock edge that data must remain stable.
Metastability: Unstable state that occurs when a flip-flop input changes close to the clock edge.
To remove metastability, use synchronization techniques like double-flopping.
Clock Domain Crossing: Transfer of signals between different clock domains, requiring careful design to avoid issues.
Blocking Assignment: Executes sequentially, can lead to race conditions if not managed properly.
Non-blocking Assignment: Executes in parallel, helps avoid race conditions and is preferred in sequential logic.
Gray Counter: A binary counter where two successive values differ in only one bit, reducing errors in state transitions.
Carry Look Ahead Adder: An adder that improves speed by calculating carry bits in advance rather than waiting for propagation.