PPO interview for SSIR (hardware) 2021: Background: IIT (old), dual degree, ECE 1. Puzzles from GFG (top 50) 2. Mod n counter, up/down counter design 3. Frequency divider: f/2, f/1.5, f/3, f/2.5, f/5, f/7, etc ; Duty cycle: 50%, 20%, 33%, etc (IMPORTANT) 4. Verilog code for: FF, latch, Adder, frequency divider, mod-n counter, MUX 5. 2:1 MUX using gates (XOR, NOT, AND, OR) 6. Encoder, decoder, MUX, deMUX + verliog 7. FSM: mealy, moore + Verilog 8. Basics of MOS, CMOS, power reduction techniques: MTCMOS, VTCMOS. 9. Metastability, Clock-domain-crossing (to be safe), STA 10. Hazards, clock-gating (to be safe) 11. basics of OOPS: polymorphism, encapsulation, etc (if you have time, just go thru definitions; pretty sure they will not ask this) 12. CV : MOST IMPORTANT: Ask about projects