1)Equations of Cordic, Block diagram, and asked me to write code in verilog for Cordic 2)Digital testing : how my minimum test cases are required to tell whether a particular(he drew a circuit) ckt is faulty or not. 3)minimum 10 rules of verilog 4) Can loops be synthesizable in verilog what about, if else what ckt will it represent 5)timing diagram with inertial delay propogation delay 6) what is Digital pre Distortion? 7) real life eg of melay moore