3 2 hour interviews were taken( Total 6 hours with 1 people in each round). Questions: how we can reduce test time. how serial chain patterns are solved. How T24 violations are debugged, how we can find which 2 flops have hold violation when we are running edt bypass patterns( initially reset all the scan flops in the chain and then shift non reset value. If at a particular cycle 2 consecutive flops get non reset value then you have found the hold violation source and sink flops). How was the architecture in my design. How was the clock architecture in my design. Detailed question on post silicon debugs (about the issues I have faced) . Limitations of wrapper cell ( scan enable signals are different for core and wrapper, during atspeed intest functional path cannot be tested).