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Open Silicon Research Asic Design Verification Engineer salaries in India

Annual salary range
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₹10.7 Lakhs - ₹13.7 Lakhs
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Avg. annual salary (AmbitionBox Estimate)
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Last Updated: 11 Mar 2023

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Asic Design Verification Engineer salary at Open Silicon Research ranges between ₹10.7 Lakhs to ₹13.7 Lakhs per year for employees with 2 years of experience. Salary estimates are based on 1 latest salaries received from various employees of Open Silicon Research.

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Open Silicon Research Asic Design Verification Engineer Salary FAQs

How the salary growth look like for a Asic Design Verification Engineer at Open Silicon Research in India?
The salary growth for a Asic Design Verification Engineer at Open Silicon Research depends on factors such as experience, performance, and promotions. On average, a Asic Design Verification Engineer can expect the following growth trajectory at Open Silicon Research:

Experience Average Salary Range
2 years ₹10.7 Lakhs to ₹13.7 Lakhs per year
and so on.

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Open Silicon Research Asic Design Verification Engineer salary in India ranges between ₹10.7 Lakhs to ₹13.7 Lakhs. This is an estimate based on latest salaries received from employees of Open Silicon Research.