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Maxim Integrated

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4.4

based on 66 Reviews

24 Maxim Integrated Jobs

Design Verification Engineer

Maxim India Integrated Circuit Design Pvt Ltd.

4.4

based on 66 Reviews

2-5 years

Bangalore / Bengaluru

1 vacancy

Design Verification Engineer

Maxim Integrated

posted 6d ago

Job Role Insights

Flexible timing

Key skills for the job

Hospital VLSI C++ Analytical Chemistry Semiconductor Perl

+ 4 more

Job Description

The Engineering Enablement Org is part of the CTO at Analog Devices and is responsible for providing Tools, Flows, Methodologies and Support to engineering teams across the company to accelerate product development. This position is for an opening in the Systems Verification and Validation (SVV) team within the Engineering Enablement org, focused on the Verification IP and Testbench Generator Development. Overall, SVV team works to define and promote the adoption of verification best practices, including Metric-Driven Verification, UVM, Verification IP, DV tools, Formal, FuSa, Security, Portable Stimulus, Emulation and FPGA prototyping technologies.

Job Responsibilities

Contribute to the development of ADIs best-in-class Testbench Generator solution to build ready to simulate IP/(sub)system-level unified testbenches for Digital, DMS and AMS.
Architect, design and develop best-in-class SV/UVM based Simulation, Accelerated and Assertion based Verification IPs for latest generation complex protocols
Support engineering DV teams to adopt in-house VIPs (including AVIP, ABVIP) and Testbench Generator, create protocol training materials, assist in debugging VIP/protocol issues
Develop reusable protocol specific Conformance Test Suite (CTS), Spec annotated Verification plan (vPlan), PSS compatible sequences and user-guide.
Explore new methodologies to improve the existing solutions further.

Job Requirements

MTech in VLSI/Electronics/Electrical Engineering with 1+ years of relevant industry experience (or) BTech with 3+ years of experience (or equivalent experience).
VIP development and/or IP/Sub-system/SOC verification experience is preferred
Strong in digital design, digital verification fundamentals, SV, SVA, UVM and MDV.
Proficient in Python/Perl (C/C++ is a plus)
Strong analytical, problem-solving and debugging skills
Highly motivated and team player

Nice to have

Exposure and technical familiarity with commonly used protocols - AMBA, SPI, I2C, etc
Exposure to hardware emulation platform (Palladium/Veloce/Zebu)
Exposure to simulators (XLM/VCS etc), version control software (P4, GIT, etc) and IDE (DVT, etc)