Senior Performance Optimization Engineer

Technical validation lead of Intel SoCs performance and PM. Would be responsible to meet PnP KPIs that meets marketing requirements by incorporating all the industry best practices of pre and post silicon verification. Candidate would interface with various stakeholders and reduce the time to productize SoC in final application.

Responsibilities and Duties

Successful candidate would:

• Drive definition of workloads, both synthetic, industry standard and customer use case specific that proves superior performance of SoC.
• Analyse trade-offs between power consumption and performance metrics that optimizes SoC RoI for the customer/
• Drive pre-Si to post-Si correlation in line with industry best in class numbers.
• Contribute towards system level specifications by collaborating with architects and product line managers.
• Provide technical oversight and management for Power Management and Performance optimization.
• Come up with design of experiments for concurrencies that hits max performance-power curves.
• Create, define and develop system validation environment and test suites for PnP. Use and apply platform level tools and techniques to ensure peak power are to spec.
• Drive methodologies to validate performance KPI in pre-Si, including optimum mechanism of RTL simulation, emulation, system-C that enhances coverage while at the same time reducing execution time.
• Define test plan by collaborating with design, internal workgroups, industry standards and 3rd party component specifications.
• Work with customer facing teams to define the metrics of success that goes beyond legacy tests.
• Write and review scripts that controls test and measurement equipment, thermal controller, silicon configuration and other test components.
• Define test plan by collaborating with design, internal workgroups, industry standards and 3rd party component specifications.
• Active involvement in technical discussions and collaboration with functional validation hardware teams and SW/FW teams for dependency tracking and root cause of complex issues.
• Strong written and verbal communication skills.

Minimum Requirements

• B.E/B.Tech degree or M.E/M.Tech degree with 7 years+ in electrical engineering and computer architecture.
• Wide exposure to industry standard benchmarks and tuning SoC that maximizes scores.
• Good knowledge of simulating industry workloads in pre-silicon environment.
• Proven expertise in debugging complex SoC problems in the platform.
• Strong BIOS / firmware expertise.
• Candidate should have excellent hands-on silicon and platform debug skills.
• Should have been responsible for performing hands-on tuning of compute core, fabric, high speed IO bandwidth and latency.
• Deep understanding of concurrencies that hyperscale compute systems would be subjected and tuning config parameters that helps achieve best in industry performance.
• Hands-on experience with C-state and P-state parametric tuning.
• Mentor junior engineers and proven skills of completing execution with contractors.

Additional Preferred Qualifications

• Ethernet protocols and its impact on compute core performance.
• Knowledge of Intel tools to create synthetic test content for power, performance and functionality of various core and peripherals / IO.
• Experienced writing Python code to automate test procedures.
• Exposure to performance scaling estimations while increasing core counts.
• System-C expertise.