DFT Engineer - ATPG Verification (8-10 yrs)

Job Description :

The Senior DFT Engineer ATPG Verification is responsible for seamlessly integrating and meticulously verifying cutting-edge DFT techniques, including scan design, boundary scan, and built-in self-test (BIST), into the design of semiconductor chips.

This role requires an in-depth understanding of DFT techniques and the ability to apply them with precision to ensure optimal testability and manufacturability of the chips.

Responsibilities :

- Collaborate closely with the design team to seamlessly integrate DFT techniques into chip design.

- Develop and execute ATPG test patterns for comprehensive functional and structural testing.

- Implement advanced scan compression techniques to minimize test data volume and test time.

- Ensure flawless operation of boundary scan and BIST features.

- Collaborate with the verification team to effectively debug and resolve DFT-related issues.

- Stay abreast of the latest advancements in DFT techniques and propose enhancements to elevate testability.

Requirements :

- Bachelor's or Master's degree in Electrical Engineering or Computer Science.

- Proven experience of 6 to 10 years in seamlessly integrating DFT techniques.

- Demonstrated expertise in UNIX/Linux and scripting languages (e.g , TCL, cshell, Perl).

- Proficient in HDL design language.

- Extensive knowledge of scan design, boundary scan, and BIST.

- Proficiency in developing ATPG test patterns.

- Familiarity with ASIC design and verification.

- Experience with advanced scan compression techniques.

- Familiarity with JTAG interface.

- Exceptional problem-solving and debugging skills.

- Strong communication and teamwork abilities.