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Physical Design Engineer - RTL (10-15 yrs)

10-15 years

Physical Design Engineer - RTL (10-15 yrs)

Coders Brain

posted 2mon ago

Job Role Insights

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Job Description

Job Title : Physical Design (PD) Engineer

Experience : 10-15 Years

Location : Bangalore / Hyderabad

Job Description :


Role Overview :

We are seeking a highly experienced Physical Design (PD) Engineer with expertise in Cadence Innovus and lower node technologies (<5nm). The candidate should have a robust background in physical design for advanced technology nodes and experience working in Samsung Foundry or equivalent environments.

Key Responsibilities :

1. Physical Design Implementation :

2. Handle RTL-to-GDSII flow, including synthesis, floorplanning, placement, clock tree synthesis (CTS), routing, and post-route optimizations.

3. Work on designs involving lower technologies (<5nm).

Tool Expertise :

1. Use Cadence Innovus extensively for design implementation and optimization.

2. Optimize designs for power, performance, and area (PPA) while adhering to design constraints.

Process Node Expertise :

1. Manage physical design challenges unique to advanced technology nodes (<5nm), including power integrity, timing closure, and signal integrity.

2. Collaborate with foundries like Samsung Foundry for process-specific design requirements.

Timing Closure and Sign-Off :

1. Perform static timing analysis (STA) and resolve timing violations.

2. Conduct physical verification checks (DRC, LVS) and power analysis using industry-standard tools.

Collaboration :

1. Work closely with the RTL design, synthesis, and sign-off teams to ensure successful tape-outs.

2. Provide mentorship and guidance to junior team members.

Required Skills :

1. Proficiency in Cadence Innovus for physical design.

2. Strong experience with lower technologies (<5nm).

3. Deep understanding of timing closure, signal integrity, power integrity, and design constraints.

4. Familiarity with Samsung Foundry processes is a must.

5. Excellent analytical and debugging skills for resolving physical design issues.

Desired Skills :

1. Knowledge of power intent tools (UPF/CPF).

2. Expertise in clock and power domain crossing checks.

3. Proficiency in scripting languages like Tcl or Perl for automation.

Key Attributes :

1. Strong problem-solving and debugging skills.

2. Excellent team collaboration and communication skills.

3. Proven ability to meet tight schedules with high-quality deliverables.


Functional Areas: Other

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