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Senior Engineer, Digital Design Engineer
4-8 years
Bangalore / Bengaluru
1 vacancy
Senior Engineer, Digital Design Engineer
Maxim Integrated
posted 3mon ago
Job Role Insights
Flexible timing
Key skills for the job
Job Description
- Work closely with the Architecture team to develop detailed specification, uArch and development plans ,
- Design key digital blocks such as accelerators/ datapath IP in Verilog/ System Verilog with built-in configurability to allow Power/ Performance/ Area tradeoffs
- Develop strong understanding of heterogenous processor cores & subsystems (ARM / RISC-V/ DSP core, and associated infrastructure such as caches, interconnect fabric, GIC, DMA, MMU, Coresight Debug & Trace, TZC, SMPU, SPU) and their integration requirements
- Develop User Guides for RTL Integration, Synthesis, Lint/CDC waivers, DFT, PnR, Programming Sequence, characterization etc.
- Evaluate 3rd party IPs on Power/ Performance/ Area (PPA) and other key qualitative aspects such as design quality, Design For Testability, robustness of Design Verification (DV) practice, ease of integration and make recommendations.
- Provide technical leadership and guidance to small teams of Micro-architects/RTL developers working on an SoC
- Work closely with the verification team for vPlan reviews and for complex debugs to resolve verification failures.
- Participate in design specification, micro architecture and verification sign off reviews.
- Improve flows and methodologies to streamline IP development and integration
- Build (including recruiting and interviewing) development teams
- Minimum B.E. / B.Tech degree in Electrical/Electronics/Computer science
- 4 -8 years of digital logic design and hands-on RTL coding experience using Verilog and SystemVerilog
- Strong understanding of control path and data-path digital design concepts with an eye for realizing correct by construction solutions
- Experience with specifying Design Verification (DV) requirements such as test plans, coverage metrics, and evaluate DV quality so as to realize robust design quality
- Knowledge of Lint, CDC, formal equivalence, DFT concepts, power analysis
- Experience with developing timing constraints and ability to carry out logic synthesis and Static timing analysis
- Good interpersonal, teamwork and communication skills to logically & effectively drive discussions with teams spread geographically
- Understanding of standard on-chip interfaces such as APB/AHB/AXI/ Stream protocols is a strong plus
- Knowledge of Processor/SoC architecture and/or DSP fundamentals is a strong plus
- Experience with end-to-end ASIC/ SoC product development & productization is very desirable
Employment Type: Full Time, Permanent
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