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Senior Post Silicon ATE Test Engineer

5-10 years

Bangalore / Bengaluru

Senior Post Silicon ATE Test Engineer

Intel

posted 21d ago

Job Role Insights

Flexible timing

Job Description

Drives and develops testability and manufacturability of integrated circuits from the component feasibility stage through production ramp. Contributes to design, development, and validation of testability circuits, test flows, and methodologies for new products through evaluation, development, and debug of complex test methods. Interfaces with process development, fab, factory, assembly, quality and reliability, and manufacturing groups to enable postsilicon HVM ramp. Evaluates new designs on automatic test equipment (ATE) and works with the design, DFx, and product development teams to debug functionality and performance issues to root cause.

Performs ATE device characterization, utilizes that data to define datasheet specifications and performs yield analysis. Collaborates with designers to drive design for test/debug/manufacturing (DFT/DFD/DFM) features enabling efficient production testing of new products.

Develops and debugs complex software programs to convert design validation vectors and drive complex test equipment. Creates and tests validation and production test hardware solutions. Tests, validates, modifies, and redesigns circuits to guarantee component margin to specification. Analyzes and evaluates component specification versus performance to ensure optimal match of component requirements with production equipment capability with specific emphasis on yield analysis and bin split capability.

Ensures manufacturability over process and product design through thorough analysis of process and spec corners and works with design to resolve yield issues before manufacturing ramp. Drives test time reduction through analysis of fallout data versus test time for various IPs to balance and drive overall product cost optimizations. Analyzes early customer returns with emphasis on driving test hole closure activities. Creates and applies concepts for optimizing component production relative to both quality and cost constraints. Leads and drives manufacturing readiness from fab, assembly, and test factory to support engineering sample and customer sample generation (ES milestones), wafer start planning, product qual execution strategy and capacity analysis, and assembly and test site certification activities.

Works with fab, assembly, and test factory partners and planners to support production ramp. May also manage execution of new product introductions in the fab, fab process targeting, product/process optimizations, and participate in factory task forces to bring product perspective and respond to product issues. Optimizes product supply through data analysis of postsilicon binsplit, die level cherry pick (DLCP), and optimize sort/test content and yield downstream through data analysis.

Qualifications

Candidate should possess a Bachelors or Master degree in Computer/ Electrical/Electronic Engineering with about 5-12 years of experience.Strong Experience of ATE Test Engineering.

  • Strong knowledge of DFT architecture, design, methodologies and tools - Analog DFT, JTAG, etc.
  • Good understanding of Test Engineering and tester debug is desirable.
  • Hands on design/validation experience with strong/proven debug skills.
  • Expertise in Advantest 93K, ATE, Test Engineering.
  • Experience in Teradyne Ultraflex, J750 etc.
  • A very good team player with good interpersonal, planning and excellent communication skills.
  • Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

Employment Type: Full Time, Permanent

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Intel Interview Questions & Tips

Prepare for Intel roles with real interview advice

Top Intel Ate Testing Engineer Interview Questions

Q1. What are the conditions for an RC circuit to work as an integrator/differentiator Can you derive it with this circuit
Q2. What are second order effects in CMOS. Can you explain each one?
Q3. How would you clear the 7th bit in a 32 bit register
View all 156 questions

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Intel Benefits

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136, HAL Old Airport Rd, Kodihalli, Bengaluru, Karnataka 560017, India Bengaluru
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