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2 Maxim Integrated Design & Verification Engineer Jobs

Senior Engineer, Design Verification Engineering

3-6 years

Bangalore / Bengaluru

1 vacancy

Senior Engineer, Design Verification Engineering

Maxim Integrated

posted 2mon ago

Job Role Insights

Flexible timing

Job Description

Senior Mixed-Signal DV Engineer
About Us
The Engineering Enablement team provides industry-leading tools, methodologies, and support to accelerate product development across the company. This position is part of the Systems Verification and Validation (SVV) team within the Engineering Enablement organization in the CTO Office. SVV is responsible for developing, adopting, and supporting tools, methodologies, and solutions across the entire DV landscape - including Unified Metric-Driven Verification (MDV), SystemVerilog (SV)/UVM-based methods, Mixed-Signal DV, Formal Verification, Functional Safety, Security, Portable Stimulus, and Emulation/Prototyping technologies.
The Opportunity
The SVV team is looking for a self-motivated individual with proven experience in analog behavioral modeling and mixed-signal design verification, along with strong analog design fundamentals to contribute to the Mixed-Signal DV domain. This role will give this individual an opportunity to work with BUs spanning ADIs breadth of industry-leading mixed-signal product portfolio and make significant impact.
Job Responsibilities:
  • Develop, deploy, and support Design Verification methodologies with a special focus on Analog/Mixed-Signal and Low-Power
  • Champion state-of-the-art circuit simulation and behavioral modeling tools and techniques, and apply to complex A/MS SoC designs with an emphasis on low-power
  • Provide high quality proactive application engineering support for both in-house and commercial EDA tools and flows
  • Assess, implement, and coordinate the development of new capabilities in the A/MS Design Verification and ensure the success of IC design teams.
Position Requirements
  • B. Tech. required, M. Tech. preferred with strong fundamentals in IC circuit design of ADCs, DACs, RF Transceivers, Voltage Regulators etc.
  • Proven skills in analog IC design and behavioral modeling are required.
  • Proficiency with EDA tools and Design Verification methodologies for low-power, mixed-signal ICs including schematic capture, layout, simulation, familiarity with low-power intent (CPF/UPF/IEEE-1801) and A/MS behavioral modeling is highly desirable.
  • Exposure to CAD tool development, experience in software programming (C++, Perl, Python) and behavioral modeling (SystemVerilog RNM, Verilog-AMS, Verilog-A) is a plus.
  • Should be able to communicate technical details very effectively with both customers (circuit designers) and peers.
Job Req Type: Experienced
Required Travel: No
Shift Type: 1st Shift/Days

Employment Type: Full Time, Permanent

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What Design & Verification Engineer at Maxim Integrated are saying

What Maxim Integrated employees are saying about work life

based on 66 employees
90%
90%
58%
100%
Flexible timing
Monday to Friday
No travel
Day Shift
View more insights

Maxim Integrated Benefits

Health Insurance
Cafeteria
Work From Home
Team Outings
Soft Skill Training
Free Transport +6 more
View more benefits

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